| 000 | 00552nam a2200169Ia 4500 | ||
|---|---|---|---|
| 003 | IN-BaIIA | ||
| 008 | 211028s9999 xx s 000 0 eng d | ||
| 020 | _a9781628416695 (Online) | ||
| 020 | _a9781628419054 (Print) | ||
| 040 | _cIIA Library | ||
| 100 |
_aVaidyanathan, Kaushik _940860 |
||
| 245 | 0 |
_aDesign Technology Co-Optimization in the Era of Sub-Resolution IC Scaling _h[eBook] |
|
| 260 |
_aWashington, USA _bSPIE _c2016 |
||
| 300 | _aOnline resource | ||
| 856 |
_uhttps://doi.org/10.1117/3.2217861 _yClick Here to Access eBook |
||
| 942 | _cEB | ||
| 999 |
_c22154 _d22154 |
||