TY  - BOOK
AU  - Vaidyanathan, Kaushik 
TI  - Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling
SN  - 9781628416695 (Online)
PY  - 2016///
CY  - Washington, USA
PB  - SPIE
UR  - https://doi.org/10.1117/3.2217861
ER  -