00754nam a2200229Ia 4500003000900000008004100009020002200050040001600072080001800088100002900106245007800135250000900213260002700222300001500249650003100264650001600295650002300311700003500334942000700369999001700376952013100393IN-BaIIA211028s9999    xx            000 0 eng d  a978-81-265-1931-6  cIIA Library  a681.3.01bPAD  aPadmanabhan, T. R935421 0aDesign through verilog HDLcT. R. Padmanabhan and B. Bala Tripura Sundari  arep.  aNew DelhibWileyc2003  axii, 455p.  aEmbeded programming935422  aVerilog HDL  aVLSI design919248  aBala Tripura Sundari, B935577  cBK  c18524d18524  00104070aBANbBANcGENd2013-02-12eSIP   g439.00l0o681.3.01/ PADp19446r2021-11-05v439.00w2013-02-12yBKGRs. 439.00